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[VHDL-FPGA-Verilog] alu_32_bit

Description: 用Verilog编写的32位ALU（运算器），具有与、或逻辑运算；加、减算术运算；小于置一，零检测，以及溢出检测等功能。其中加法运算是采用了快速进位链-32bitALU
Platform: | Size: 2048 | Author: zhyan | Hits:

[Other] ALU_function

Description: ALU function for verilog
Platform: | Size: 132096 | Author: Seungyun | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[VHDL-FPGA-Verilog] aluN

Description: One simple Alu with 8 bits in verilog
Platform: | Size: 3072 | Author: guilherme | Hits:

[VHDL-FPGA-Verilog] ALUC

Description: 用verilog语言中xilinx平台上实现single ALU,包括alu的基本MIPS指令运算,ALU control的实现-Xilinx verilog languages with the platform to achieve single ALU, including the basic MIPS instructions alu operations, ALU control implementation
Platform: | Size: 2069504 | Author: 何进 | Hits:

[Embeded-SCM Develop] alu_sequence_detector_1101

Description: It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
Platform: | Size: 1024 | Author: urvish | Hits:

[VHDL-FPGA-Verilog] Project_III

Description: 16bit的ALU，完成加减乘数移位功能，使用verilog编写-16bit the ALU, multiplier displacement function to complete the addition and subtraction, using verilog write
Platform: | Size: 1656832 | Author: wqwq | Hits:

[VHDL-FPGA-Verilog] m.e-lab

Description: vhdl verilog code for alu operation pll,biy sliced processor
Platform: | Size: 6144 | Author: suganya | Hits:

[VHDL-FPGA-Verilog] Lab4

Description: Lab 4 Verilog implementation of ALU
Platform: | Size: 144384 | Author: Billy Bob | Hits:

[VHDL-FPGA-Verilog] ALUPVERILOG

Description: 用verilog HDL语言实现ALU 运行于quartus-ALU using verilog HDL language to run on quartus
Platform: | Size: 1170432 | Author: chenyu | Hits:

[VHDL-FPGA-Verilog] jf

Description: verilog编写的alu模块4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出-Verilog modules prepared by the ALU4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: 王川 | Hits:

[VHDL-FPGA-Verilog] SRC

Description: 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
Platform: | Size: 2048 | Author: 吴慧 | Hits:

[VHDL-FPGA-Verilog] F_ADD

Description: 使用硬體描述語言verilog的運算單元-it s an ALU using verilog to design
Platform: | Size: 2048 | Author: sky | Hits:

[VHDL-FPGA-Verilog] SourceCode

Description: That s a bunch of ALU control code for MIPS pipelined in Verilog!
Platform: | Size: 3072 | Author: baocatsamac_77 | Hits:

[Other] final-project

Description: Verilog 的Branch和Jump指令的实现 添加了MUX和额外的ALU-Verilog Branch and Jump instructions achieve add the MUX and additional ALU
Platform: | Size: 435200 | Author: Xin wang | Hits:

[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog

Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Platform: | Size: 9216 | Author: 张昊溢 | Hits:

[Embeded-SCM Develop] alu_sequence_detector_1101

Description: It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
Platform: | Size: 1024 | Author: ddeInde | Hits:

[Other] cluster

Description: ALU Cluster using VERILOG.
Platform: | Size: 4096 | Author: Anand Mehta | Hits:

[Embeded-SCM Develop] alu_sequence_detector_1101

Description: It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
Platform: | Size: 1024 | Author: 杜兰特 | Hits:

[Algorithm] day8_alu_design

Description: this verilog code for designing ALU in fpga.-this is verilog code for designing ALU in fpga.
Platform: | Size: 145408 | Author: gaurav | Hits:
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